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| (R) STP5NB100 STP5NB100FP N - CHANNEL 1000V - 2.4 - 5A - TO-220/TO-220FP PowerMESHTM MOSFET T YPE STP5NB100 STP5NB100F P V DSS 1000 V 1000 V R DS(on) < 2.7 < 2.7 ID 5A 5A TYPICAL RDS(on) = 2.4 EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED VERY LOW INTRINSIC CAPACITANCES GATE CHARGE MINIMIZED 1 3 2 3 1 2 DESCRIPTION Using the latest high voltage MESH OVERLAYTM process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performances. The new patent pending strip layout coupled with the Company's proprietary edge termination structure, gives the lowest RDS(on) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charge and switching characteristics. APPLICATIONS HIGH CURRENT, HIGH SPEED SWITCHING SWITCH MODE POWER SUPPLIES (SMPS) DC-AC CONVERTERS FOR WELDING EQUIPMENT AND UNINTERRUPTIBLE POWER SUPPLIES AND MOTOR DRIVE ABSOLUTE MAXIMUM RATINGS Symb ol V DS V DGR V GS ID ID I DM (*) P tot dv/dt(1) V ISO T s tg Tj Parameter Drain-source Voltage (V GS = 0) Drain- gate Voltage (R GS = 20 k) G ate-source Voltage Drain Current (continuous) at T c = 25 C Drain Current (continuous) at T c = 100 C Drain Current (pulsed) T otal Dissipation at T c = 25 C Derating Factor Peak Diode Recovery voltage slope Insulation W ithstand Voltage (DC) Storage Temperature Max. Operating Junction Temperature o o o TO-220 TO-220FP INTERNAL SCHEMATIC DIAGRAM Value ST P5NB100 STP5NB100FP 1000 1000 30 5 3.1 15.2 135 1.08 4.5 -65 to 150 150 (1) ISD 5 A, di/dt 200 A/s, VDD V(BR)DSS, Tj TJMAX Unit V V V 5(*) 3.1(*) 15.2 40 0.32 4.5 2000 A A A W W/ o C V/ns V o o C C (*) Pulse width limited by safe operating area (*) Limited only by maximum temperature allowed February 2000 1/9 STP5NB100/STP5NB100FP THERMAL DATA TO-220 R thj- ca se R t hj-a mb R thc -sin k Tl Thermal Resistance Junction-case Max 0.93 62.5 0.5 300 TO-220F P 3.12 o o o C/W C/W C/W o C Thermal Resistance Junction-ambient Max Thermal Resistance Case-sink Typ Maximum Lead T emperature F or Soldering Purpose AVALANCHE CHARACTERISTICS Symbo l I AR E AS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Single Pulse Avalanche Energy o (starting T j = 25 C, ID = I AR , VDD = 50 V) Max Valu e 5 220 Unit A mJ ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF Symbo l V ( BR)DSS I DSS I GSS Parameter Drain-source Breakdown Voltage Test Cond itions ID = 250 A V GS = 0 Min. 1000 1 50 100 Typ . Max. Un it V A A nA VDS = Max Rating Zero Gate Voltage Drain Current (V GS = 0) VDS = Max Rating Gate-body Leakage Current (V DS = 0) VGS = 30 V Tc = 125 C o ON () Symbo l V GS(th ) R DS(on ) I D(on) Parameter Gate T hreshold Voltage Static Drain-source On Resistance VDS = V GS VGS = 10 V Test Cond itions ID = 250 A I D = 2.5 A 5 Min. 3 Typ . 4 2.4 Max. 5 2.7 Un it V A On State Drain Current VDS > I D(on ) x R DS(on )max VGS = 10 V DYNAMIC Symbo l g fs () C is s C os s C rs s Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Tr ansfer Capacitance Test Cond itions VDS > I D(on ) x R DS(on )max VDS = 25 V f = 1 MHz I D = 2.5 A VGS = 0 Min. 1.5 1500 150 17 Typ . Max. Un it S pF pF pF 2/9 STP5NB100/STP5NB100FP ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbo l t d( on) tr Qg Q gs Q gd Parameter Turn-on T ime Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Cond itions VDD = 500 V I D = 2.5 A VGS = 10 V R G = 4.7 (see test circuit, figure 3) VDD = 800 V I D = 5 A V GS = 10 V Min. Typ . 24 11 39 9.6 19.2 51 Max. Un it ns ns nC nC nC SWITCHING OFF Symbo l t r(Vof f ) tf tc Parameter Off-voltage Rise Time Fall Time Cross-over T ime Test Cond itions VDD = 800 V I D = 5 A R G = 4.7 V GS = 10 V (see test circuit, figure 5) Min. Typ . 20 22 26 Max. Un it ns ns ns SOURCE DRAIN DIODE Symbo l I SD I SDM (*) V SD () t rr Q rr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward O n Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 5 A VGS = 0 780 5.5 14 Test Cond itions Min. Typ . Max. 5 20 1.6 Un it A A V ns C A ISD = 5 A di/dt = 100 A/s Tj = 150 o C VDD = 100 V (see test circuit, figure 5) () Pulsed: Pulse duration = 300 s, duty cycle 1.5 % (*) Pulse width limited by safe operating area Safe Operating Area for TO-220 Safe Operating Area for TO-220FP 3/9 STP5NB100/STP5NB100FP Thermal Impedance for TO-220 Thermal Impedance forTO-220FP Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance 4/9 STP5NB100/STP5NB100FP Gate Charge vs Gate-source Voltage Capacitance Variations Normalized Gate Threshold Voltage vs Temperature Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics 5/9 STP5NB100/STP5NB100FP Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/9 STP5NB100/STP5NB100FP TO-220 MECHANICAL DATA DIM. MIN. A C D D1 E F F1 F2 G G1 H2 L2 L4 L5 L6 L7 L9 DIA. 13.0 2.65 15.25 6.2 3.5 3.75 0.49 0.61 1.14 1.14 4.95 2.4 10.0 16.4 14.0 2.95 15.75 6.6 3.93 3.85 0.511 0.104 0.600 0.244 0.137 0.147 E mm TYP. MAX. 4.60 1.32 2.72 1.27 0.70 0.88 1.70 1.70 5.15 2.7 10.40 0.019 0.024 0.044 0.044 0.194 0.094 0.393 MIN. 0.173 0.048 0.094 4.40 1.23 2.40 inch TYP. MAX. 0.181 0.051 0.107 0.050 0.027 0.034 0.067 0.067 0.203 0.106 0.409 0.645 0.551 0.116 0.620 0.260 0.154 0.151 A C D1 L2 F1 D G1 Dia. F2 F L5 L7 L6 L9 L4 G H2 P011C 7/9 STP5NB100/STP5NB100FP TO-220FP MECHANICAL DATA DIM. MIN. A B D E F F1 F2 G G1 H L2 L3 L4 L6 L7 O 28.6 9.8 15.9 9 3 4.4 2.5 2.5 0.45 0.75 1.15 1.15 4.95 2.4 10 16 30.6 10.6 16.4 9.3 3.2 1.126 0.385 0.626 0.354 0.118 mm TYP. MAX. 4.6 2.7 2.75 0.7 1 1.7 1.7 5.2 2.7 10.4 MIN. 0.173 0.098 0.098 0.017 0.030 0.045 0.045 0.195 0.094 0.393 0.630 1.204 0.417 0.645 0.366 0.126 inch TYP. MAX. 0.181 0.106 0.108 0.027 0.039 0.067 0.067 0.204 0.106 0.409 A B L3 L6 L7 F1 F D G1 E H F2 123 L2 L4 8/9 G STP5NB100/STP5NB100FP Information furnished is believed to be accurate and reliable. However, STMicroelectonics assumes no responsibil ity for the consequences r of use of such information nor for any infringement of patents or other rights of third partes which may result from its use. No license is i granted by implication or otherwise under any patent or patent rights of STMicroelectro nics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all informaton previously supplied. STMicroelectronics products i are not authorized for use as critical components in life support devices or systems with express written approval of STMicroelectronics. out The ST logo is a trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japa - Malaysia - Malta - Morocco n Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com . 9/9 |
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